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| a FEATURES Frequency Synthesis to 155.52 MHz 19.44 MHz or 9.72 MHz Input Reference Signal Select Mux Single Supply Operation: +5 V or -5.2 V Output Jitter: 2.0 Degrees RMS Low Power: 90 mW 10 KH ECL/PECL Compatible Output 10 KH ECL/PECL/TTL/CMOS Compatible Input Package: 16-Pin Narrow 150 Mil SOIC 155.52 MHz Frequency Synthesizer AD809 155.52 Mbps ports. The AD809 can be applied to create the transmit bit clock for one or more ports. An input signal multiplexer supports loop-timed applications where a 155.52 MHz transmit bit clock is recovered from the 155.52 Mbps received data. The low jitter VCO, low power and wide operating temperature range make the device suitable for generating a 155.52 MHz bit clock for SONET/SDH/Fiber in the Loop systems. The device has a low cost, on-chip VCO that locks to either 8x or 16x the frequency at the 19.44 MHz or 9.72 MHz input. No external components are needed for frequency synthesis; however, the user can adjust loop dynamics through selection of a damping factor capacitor whose value determines loop damping. The AD809 design guarantees that the clock output frequency will drift low (by roughly 20%) in the absence of a signal at the input. The AD809 consumes 90 mW and operates from a single power supply at either +5 V or -5.2 V. PRODUCT DESCRIPTION The AD809 provides a 155.52 MHz ECL/PECL output clock from either a 19.44 MHz or a 9.72 MHz TTL/CMOS/ECL/PECL reference frequency. The AD809 functionality supports a distributed timing architecture, allowing a backplane or PCB 19.44 MHz or 9.72 MHz timing reference signal to be distributed to multiple FUNCTIONAL BLOCK DIAGRAM CF1 CF2 7 8 (19.44MHz CLKIN 13 OR 9.72MHz) CLKINN 12 AUTO SELECT PFD LOOP FILTER BW ADJUST VCO TTL/CMOSIN 10 AUTO SELECT DIVIDE BY 8/16 AD809 PECLIN 2 (155MHz) PECLINN 1 MUX 15 MUX 5 4 CLKOUT CLKOUTN (155MHz PECL OUTPUT) REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 World Wide Web Site: http://www.analog.com Fax: 617/326-8703 (c) Analog Devices, Inc., 1997 AD809-SPECIFICATIONS (T = T A MIN to TMAX, VS = VMIN to VMAX, CD = 22 nF, unless otherwise noted) Min 19.42 9.71 1.6 1.6 200 0.08 0.02 15 85 Typ Max 19.46 9.73 2.9 2.9 Units MHz MHz Degrees RMS Degrees RMS kHz dB dB % Parameter TRACKING AND CAPTURE RANGE OUTPUT JITTER JITTER TRANSFER Bandwidth Peaking DUTY CYCLE TOLERANCE INPUT VOLTAGE LEVELS PECL Input Logic High, VIH Input Logic Low, VIL TTL Input Logic High, VIH Input Logic Low, VIL OUTPUT VOLTAGE LEVELS PECL Output Logic High, VOH Output Logic Low, VOL SYMMETRY (Duty Cycle) OUTPUT RISE/FALL TIMES 1.5 Rise Time (tR) Fall Time (tF) POWER SUPPLY VOLTAGE POWER SUPPLY CURRENT OPERATING TEMPERATURE RANGE 1 Condition x8 Synthesis x16 Synthesis x8 Synthesis x16 Synthesis CD = 5.6 nF ( = 5) CD = 22 nF ( = 10) x8 or x16 Synthesis Output Jitter 2.9 Degrees RMS @ CLKIN/N and PECLIN/N Inputs @ TTL/CMOSIN and MUX Inputs Referenced to VCC 3.8 3.1 2.0 VCC 3.6 Volts Volts Volts Volts 0.8 -1.2 -2.0 x8 Synthesis or x16 Synthesis 20%-80% 80%-20% VMIN to VMAX 4.5 46 -1.0 -1.8 52 -0.7 -1.7 62 Volts Volts % % ns ns Volts mA C 1.1 1.1 1.5 1.5 5.5 17 TMIN to TMAX -40 26 +85 NOTES 1 Device design is guaranteed for operation over Capture Ranges and Tracking Ranges, however the device has wider capture and tracking ranges (for both x8 and x16 synthesis). Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS* Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +12 V Input Voltage (Pin 12 or Pin 13) . . . . . . . . . . . . . . VCC + 0.6 V Maximum Junction Temperature. . . . . . . . . . . . . . . . . +165C Storage Temperature Range . . . . . . . . . . . . . -65C to +150C Lead Temperature Range (Soldering 10 sec) . . . . . . . . +300C ESD Rating (Human Body Model) . . . . . . . . . . . . . . . . 1500 V *Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristics: 16-Pin Narrow Body SOIC Package: JA = 110C/W. "ON" TIME tON OUTPUT 50% (PINS 4 & 5) PERIOD SYMMETRY = (100 x tON/) Figure 1. Symmetry ORDERING GUIDE Model AD809BR AD809BR-REEL7 Temperature Range -40C to +85C -40C to +85C -2- Package Description 16-Pin Narrow Body SOIC 750 Pieces, 7" Reel Package Option R-16A R-16A REV. A AD809 PIN DESCRIPTIONS Table I. Pin No. Mnemonic 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PECLINN PECLIN VCC2 CLKOUTN CLKOUT VCC1 CF1 CF2 AVEE AVCC1 CLKINN CLKIN AVCC2 MUX VEE MUX Input Description Differential 155 MHz Input Differential 155 MHz Input Digital VCC for PECL Outputs Differential 155 MHz Output Differential 155 MHz Output Digital VCC for Internal Logic Loop Damping Capacitor Loop Damping Capacitor Analog VEE Analog VCC for PLL PECL Differential Reference Clock Input PECL Differential Reference Clock Input Analog VCC for Input Stage Input Signal Mux Control Input Digital VEE PIN CONFIGURATION AD809 Phase Skew Input Selected CLKIN/CLKINN PECLIN/PECLINN TTL "0" TTL "1" Table II. Applying a PECL/ECL or CMOS/TTL Reference Input to the AD809 Input Reference PECL/ECL Differential AD809 Configuration Apply the valid PECL-level reference frequency to Pins 13 and 12. AD809 frequency synthesizer ignores the input at Pin 10. Apply the reference frequency to Pin 10. Connect Pins 13 and 12 to AVEE (Pins 9 and 16). The AD809 senses the common-mode signal at these pins as less than valid PECL and selects the TTL/CMOS input as active. TTL/CMOSIN TTL/CMOS Reference Clock Input TTL/CMOS Single-Ended The AD809 output is in phase with the input. The falling edge at Pin 4, CLKOUTN, occurs 700 ps before the rising edge at Pin 10, TTL/CMOSIN at 27C. The phase skew remains relatively constant over temperature. Refer to Table III for phase skew data. Table III. Phase Skew vs. Temperature PECLINN 1 PECLIN 2 VCC2 3 CLKOUTN 4 16 VEE 15 MUX 14 AVCC2 AD809 13 CLKIN TOP VIEW CLKOUT 5 (Not to Scale) 12 CLKINN VCC1 6 CF1 7 CF2 8 11 AVCC1 10 TTL/CMOSIN 9 AVEE Temperature ( C) -35 -20 0 10 30 50 70 80 90 100 Skew (CLKOUTN, Pin 4, Relative to TTL/CMOSIN, Pin 10 Measured in ps at Package Pins) -1000 -950 -850 -750 -700 -600 -450 -450 -350 -250 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD809 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE REV. A -3- AD809 DEFINITION OF TERMS Maximum, Minimum and Typical Specifications Typical Characteristic Curves AD809 FREQUENCY SYNTHESIZER JITTER DISTRIBUTION MATRIX 75 DEVICES (3 LOTS) [ECL, TTL] x [x8, x16] x [RISE, FALL] x [+4.5V, +5.0V, +5.5V] x [-40C, +25C, +85C] Specifications for every parameter are derived from statistical analyses of data taken on multiple devices from multiple wafer lots. Typical specifications are the mean of the distribution of the data for that parameter. If a parameter has a maximum (or a minimum), that value is calculated by adding to (or subtracting from) the mean six times the standard deviation of the distribution. This procedure is intended to tolerate production variations: if the mean shifts by 1.5 standard deviations, the remaining 4.5 standard deviations still provide a failure rate of only 3.4 parts per million. For all tested parameters, the test limits are guardbanded to account for tester variation to thus guarantee that no device is shipped outside of data sheet specifications. Capture and Tracking Range 1200 CUMULATIVE % 1000 THIS CHART DESCRIBES THE AD809 OUTPUT JITTER SPECIFICATION OVER MANY CONDITIONS. THE DATA REPRESENTED ARE TAKEN WITH RESPECT TO THE RISING AND FALLING EDGES, FOR EACH FREQUENCY RANGE, LOCKED TO EITHER TTL OR ECL INPUT, OVER ALL TEMPERATURE AND SUPPLY CONDITIONS. 100 90 80 70 60 50 40 30 FREQUENCY 20 10 POPULATION - Devices 600 400 200 This is the range of input data rates over which the AD809 will remain in lock. Jitter 0 0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 More RMS JITTER - Degrees This is the dynamic displacement of digital signal edges from their long term average positions, measured in degrees rms. Jitter on the input clock causes jitter on the synthesized clock. Output Jitter RMS JITTER - Degrees Figure 2. Jitter Histogram 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 19.44MHz 9 72MHz TA = +25C VCC = +5V This is the jitter on the synthesized clock (OUTPUT, OUTPUT), in degrees rms. Jitter Transfer The AD809 exhibits a low-pass filter response to jitter applied to its input data. Bandwidth This describes the frequency at which the AD809 attenuates sinusoidal input jitter by 3 dB. Peaking This describes the maximum jitter gain of the AD809 in dB. Damping Factor, 0 10 20 30 40 50 60 70 INPUT DUTY CYCLE - % 80 90 100 Damping factor, describes the compensation of the second order PLL. A larger value of corresponds to more damping and less peaking in the jitter transfer function. Duty Cycle Tolerance Figure 3. Jitter vs. Input Duty Cycle The AD809 exhibits a duty cycle tolerance that is measured by applying an input signal (nominal input frequency) with a known duty cycle imbalance and measuring the x8 or x16 output frequency. Symmetry-Recovered Clock Duty Cycle Symmetry is calculated as (100x on time)/period, where on time equals the time that the clock signal is greater than the midpoint between its "0" level and its "1" level. -4- REV. A CUMULATIVE - % 800 AD809 USING THE AD809 Ground Planes VCC1 Use of one ground plane for connections to both analog and digital grounds is recommended. Use of a 10 F capacitor between VCC and ground is recommended. Care should be taken to isolate the +5 V power trace to VCC2 (Pin 3). The VCC2 pin is used inside the device to provide the CLKOUT/CLKOUTN signals. Use of a trace connecting Pin 14 and Pin 6 (AVCC2 and VCC1 respectively) is recommended. Use of 0.1 F capacitors between IC power supply and ground is recommended. Power supply decoupling should take place as close to the IC as possible. Refer to the schematic, Figure 5, for advised connections. Transmission Lines Power Supply Connections Synthesizer Input TTL/CMOSIN 500 2*ITTL 80A OR 0A 2*ITTL 80A OR 0A VEE VCC1 7.5k 7.5k Use of 50 transmission lines are recommended for PECL inputs. Terminations Synthesizer Input CLKIN/CLKINN PECL INPUT 500 ITTL 500 40A VEE 40A Termination resistors should be used for PECL input signals. Metal, thick film, 1% tolerance resistors are recommended. Termination resistors for the PECL input signals should be placed as close as possible to the PECL input pins. Connections from the power supply to load resistors for input and output signals should be individual, not daisy chained. This will avoid crosstalk on these signals. Loop Damping Capacitor, C D 460 460 VCC2 PLL Differential Output Stage- CLKOUT/CLKOUTN 2.6mA VEE DIFFERENTIAL OUTPUT A ceramic capacitor may be used for the loop damping capacitor. A 22 nF capacitor provides a damping factor of 10. Figure 4. Simplified Schematics C1 0.1F J5 R5 301 R1 49.9 R2 49.9 50 STRIP LINE EQUAL LENGTH 16-PIN SOIC SOLDERED TO BOARD JUMPER W1 GND MUX EXT +5V R16 301 JUMPER W3 R14 49.9 R15 49.9 C13 0.1F C14 0.1F C10 R13 49.9 C15 0.1F J6 CLKIN J7 CLKINN R3 C6 100 0.1F R4 100 R11 154 R12 154 TP1 CD TP2 VECTOR PINS SPACED FOR THROUGH-HOLE CAPACITOR ON VECTOR CUPS. COMPONENT SHOWN FOR REFERENCE ONLY. C8 6 VCC1 7 CF1 8 CF2 GUARD RING NOTE: C11 10F TP4 GND C7-C10 ARE 0.1F BYPASS CAPACITORS RIGHT ANGLE SMA CONNECTOR OUTER SHELL TO GND PLANE ALL RESISTORS ARE 1% 1/8 WATT SURFACE MOUNT TPx TEST POINTS ARE VECTOR PINS AVCC1 11 TTL/CMOSIN 10 AVEE 9 J8 CMOS/TTL IN C12 0.1F J1 C2 0.1F ECL INN J2 C3 0.1F ECL IN J3 C4 0.1F CLKOUTN J4 C5 0.1F CLKOUT R6 3.65k JUMPER W2 AD809 1 PECLINN 2 PECLIN VEE 16 MUX 15 AVCC2 14 CLKIN 13 CLKINN 12 C9 R17 3.65k R7 100 R8 100 C7 3 VCC2 4 CLKOUTN 5 CLKOUT TP3 +5V Figure 5. Evaluation Board Schematic REV. A -5- AD809 Figure 6. Evaluation Board: Component Side Figure 7. Evaluation Board: Solder Side -6- REV. A AD809 Figure 8. Evaluation Board: INT2 REV. A -7- AD809 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 16-Lead Small Outline IC Package (R-16A) C2045a-2-1/97 0.0196 (0.50) x 45 0.0099 (0.25) 0.0688 (1.75) 0.0532 (1.35) 0.0098 (0.25) 0.0040 (0.10) 0.0500 (1.27) BSC 0.0192 (0.49) 0.0138 (0.35) 8 0 0.0500 (1.27) 0.0160 (0.41) 16 9 0.1574 (4.00) 0.1497 (3.80) PIN 1 1 8 0.2440 (6.20) 0.2284 (5.80) 0.3937 (10.00) 0.3859 (9.80) 0.0099 (0.25) 0.0075 (0.19) -8- REV. A PRINTED IN U.S.A. |
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